Design of wideband all-digital phase locked loops using multirate digital filter banks

摘要

All-digital phase locked loops (DPLLs) have many advantages over analog loops. However, due to digital device limitations and costs, superwide PLLs with front-end bandwidths as high as one gigahertz are commonly implemented using analog parts. This article presents a new architecture that allows an all-digital implementation of superwide PLLs. The problem of operating digital components at high speed is avoided here (without reducing the front-end bandwidths) by inserting a multirate digital filter bank in front of the DPLL. The new design is shown to have steady-state and transient performance that is identical to a conventional DPLL.