Dual-Miller Parallel Compensation for Low-Power Three-Stage Amplifier with a Wide Range of Capacitive Loads

摘要

In this paper, a dual-Miller parallel compensation (DMPC) technique for low-power three-stage amplifier is presented with detailed theoretical analysis. A feedback network realized by capacitor and transconductance is added between the first and third stage, which improves significantly the performance when driving large capacitive loads. Furthermore, it is found to be stable for a wide range of capacitive loads. The proposed DMPC amplifier has been implemented in a 0.13-μm CMOS process and the chip area is 0.17 × 0.11 mm~2. It achieves a 0.87 MHz gain-bandwidth product by consuming a total current of 41 μA. The DMPC amplifier is verified to be stable when the load capacitor ranges from 8 pF to 2 nF.