src='/images/tex/28208.gif' alt='(4+2log n)Delta G'> Parallel Prefix Modulo- src='/images/tex/28209.gif' alt='(2^n-3)'> Adder via Double Representation of Residues in [0, 2]

摘要

The most popular modulus in residue number systems (RNS), next to power-of-two modulus, are those of the form . However, in RNS applications that require a larger dynamic range, without increasing the parameter, modulus of the form are gaining popularity. Nevertheless, latency-balanced computational channels in RNS arithmetic systems are desirable. Ripple-carry modulo- adders are realized simply as one's complement adders, where serves as a second representation for 0. However, the same single -bit adder realization is not possible for modulo . Given that the efficient parallel prefix realization of modulo- adders exists, whose latency is compatible with similar modulo- adders, we are motivated to design latency-compatible parallel prefix modulo- adders. In this brief, we propose the fastest of such adders, where residues in {0, 1, 2} can be represented also as excess- encoding (i.e., , respectively) . The delay and area overhead of the proposed adder with respect to the base modulo-