Designing For Signal Visibility In Backplanes And Serial Links

摘要

Signal integrity in the design of backplanes and multi-gigabit serial links has become one of the most vexing problems in high-speed digital design. As aggregate backplane speeds exceeded 1 and 2.5 Gbits/sec in the early 21st century, designers learned that problems in planning for timing skew and trace analysis increased exponentially from slower designs. In recent years, 10 Gbit/sec Ethernet emerged as a common standard in both backplane and serial-link development, with plans for 40 and 100 Gbit follow-ons. Developers in both backplane and short-range fiber link designs have relied on physical probes and behavioral simulation to gain a necessarily limited view of signal characteristics. While test equipment companies are making every effort to increase the speed of probes into tens of gigabits per second, testing at speed has become problematic, while behavioral simulation of such high-speed links sacrifices accuracy.