Implementation of a FFT radix 2 butterfly using serial RSFQ multiplier-adders

摘要

We have designed a Decimation-in-Time (DIT) radix 2 butterfly integrated circuit. This circuit will be used to implement the 32-point Fast Fourier Transform (FFT) in a parallel data flow architecture. The radix 2 butterfly circuit uses serial RSFQ math and consists of four single bit-wide serial multipliers and eight carry-save serial adders. The circuit with 16-bit word-length employs only 3400 junctions, occupies an area of 3.8/spl times/2.0 mm/sup 2/, and dissipates less than 1.1 mW power. The multiplier is implemented using the unique RSFQ bit-clock-pipelined schema. We have successfully tested a library of serial multiply-add elements: the 8-bit multiplier at 6.3 GHz and adders with dc bias margin /spl plusmn/20%. Finally, we have demonstrated full operation of the radix 2 butterfly chip with 5-bit word length.