High-speed decimation filter for delta-sigma analog-to-digital converter

摘要

A 12-bit digital filter is designed for an A/D converter system with sampling speed of 16 GHz. Data stream of 16 Gbit/s from delta-sigma modulator will pass through a 1:4 demultiplexer. Four identical 12-bit digital filters are used to catch the data streams from the demultiplexer for 4 Gbit/s in each channel. The 12-bit superconductive digital filter is designed with modified variable threshold logic (MVTL) gates. A novel XOR gate is designed and used in this circuit to reduce circuit complexity and improve performance. Progress of high speed testing results is presented. The filter comprises 584 Josephson junctions and consumes about 1 mW power.