A low power sigma-delta modulator for dual-mode wide-band receiver

摘要

This work presents a low power cascaded sigma-delta modulator for GSM and WCDMA applications. The proposed modulator has the characteristics of wide bandwidth for WCDMA applications and low distortion in the low frequency band for GSM applications. Low-distortion and interpolative techniques are used in this modulator to enhance the performance. The low-distortion technique has not only the swing-suppressing characteristic, but it can reduce the power consumption. Moreover, the resolution can be improved even under non-linearity effects. An experimental chip is implemented in the standard 0.18-μm 1P6M CMOS technology. The measurements indicate a dynamic range of 76/68 dB and a peak signal to noise plus distortion ratio of 70/61 dB for GSM/WCDMA applications. The core area is 1 × 1.4 mm2 and the power consumption is 10.5/28 mW for GSM/WCDMA at 1.8 V.