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Novel Method of Separating Probe and Wire Bond Regions Without Increasing Die Size and Reducing Weak Fab-BEOL Adhesion Interfaces

机译:分离探针和引线键合区域而不增加芯片尺寸并减少弱Fab-BEOL粘合界面的新方法

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摘要

The drive for enhanced electrical performance and reduced silicon area has triggered significant changes in wafer fabrication, wafer level testing, and packaging technologies. In the wafer fabrication era, copper is quickly replacing aluminum as the interconnect metal of choice for technologies 0.13μm and below. To overcome the difficulty of wire bonding onto readily oxidized copper bond pads, capping copper bond pads with aluminum has been the industry standard method for wire bonding. In terms of wafer level testing and packaging, the resulting me pitch geometry has created challenges for both cantilever probe and wire bond processes. Pad damage due to probe marks during probe process has been shown to cause "non-sticks" and "lifted bonds" at the wire bonding process. The wire bond yield loss due to pad damage is aggravated for fine pitch since increasingly smaller bonded ball diameters are formed on top of the same damage area caused by the probe mark. Wire Bond parameter optimization can minimize wire bond yield loss but cannot eliminate the problem. One logical solution is to lengthen the bond pad to create separate regions for probing and wire bonding. However, this method can result in a larger die size. This paper will reveal a unique bond pad structure that provides separate regions yet results in no impact to the existing die size. This bond pad structure utilizes the aluminum cap layer to create a longer bond pad without changing the size of the underlying copper last metal, resulting in no impact to the existing die size. Evaluations were conducted on 0.13μm CMOS technology, with cantilever probing and wire bonding on 52μm bond pad size. Failure analysis and test methods to detect failures will be discussed. Designs of experiments for probing and wire bonding processes, characteriza-tion studies, and reliability results will be presented. Furthermore, a unique Extended Armored Pad (EAP) has been introduced for the purpose of reduc-ing the Ta-Cu interface area under the Aluminum bond pad region because the Ta-Cu adhesion is known to be one of the weakest interfaces for Cu-interconnect BEOL processes.
机译:增强电气性能和减小硅面积的驱动力引发了晶圆制造,晶圆级测试和封装技术的重大变化。在晶圆制造时代,铜正在迅速取代铝,成为0.13μm及以下技术的首选互连金属。为了克服将引线键合到易氧化的铜键合焊盘上的困难,用铝覆盖铜键合焊盘一直是引线键合的工业标准方法。在晶圆级测试和封装方面,最终的间距几何形状对悬臂式探针和引线键合工艺都提出了挑战。已表明,在探针焊接过程中由于探针痕迹造成的焊盘损坏会在引线键合过程中导致“不粘”和“剥离”。对于细间距,由于焊盘损坏而导致的引线键合良率损失会增加,因为在由探针标记引起的相同损坏区域的顶部形成的焊球直径越来越小。引线键合参数优化可以最大程度地减小引线键合良率损失,但不能消除问题。一种合理的解决方案是加长焊盘,以创建用于探测和引线键合的单独区域。但是,这种方法会导致更大的芯片尺寸。本文将揭示一种独特的焊盘结构,该结构可提供单独的区域,但不会影响现有的芯片尺寸。这种键合焊盘结构利用铝盖层来创建更长的键合焊盘,而不会改变底层铜最后金属的尺寸,因此不会影响现有的芯片尺寸。在0.13μmCMOS技术上进行了评估,其中悬臂式探针和引线键合在52μm的焊盘尺寸上进行。将讨论故障分析和检测故障的测试方法。将介绍用于探测和引线键合过程的实验设计,表征研究以及可靠性结果。此外,为了减少铝键合焊盘区域下方的Ta-Cu界面面积,引入了独特的扩展装甲焊盘(EAP),因为众所周知Ta-Cu附着力是Cu-的最弱界面之一。互连BEOL流程。

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