D Technology with Application to High Bandwidth and Processor-Memory Modules

摘要

Performance improvement of semiconductors through device scaling is decreasing from generation to generation. Three dimensional (3D) chip stacking technology is now an available option to increase the effective performance of a system. IBM has developed node-agnostic Cu through silicon vias (TSVs) integrated with high-K dielectric/metal gate and embedded DRAM as part of our 3D technology offering. Thermal cycling and stress results show no degradation of TSV or interconnect structures. Device and functional data indicate that there is no significant impact from TSV processing and proximity effects to adjacent structures. A multichip module package has been designed in IBM's 3D silicon technology with embedded TSVs that showcases the advantages of 3D for large bandwidth chip to chip links. The module consists of two chips of the same size and type communicating horizontally through a silicon in-terposer to a large ASIC chip. The chip to chip links operate at 8 Gbps with a loss of 0.5 dB/mm. Model to hardware correlation was performed on the links, and trace loss is within 0.1 dB of modeling data. Both input and output signals of the module go up or down through TSVs in the silicon interposer as part of their electrical paths. TSV parameters do not limit the electrical performance of the module. Memory and processor applications are also good candidates for applying 3D. IBM has also developed active chip stacking technology to enable clients to design 3D semiconductors with large amounts of memory and logic for their end products.