Your IMAPS Member Benefits at Your Chapter Level

摘要

The Arizona IMAPS chapter kicked off what is planned to be a busy 2016 calendar of events on January 14th with a luncheon presentation titled Enabling a New Class: The Panel Level SoC from Tim Olson, Founder and Chief Technology Officer of Deca Technologies. Chapter officers put this event together in just a few weeks, so were pleased to have 60 attendees and 2 exhibitors. The high interest in fan-out wafer level package (FO-WLP) technology and quality of the presentation were key factors in proceeding with an event on short notice. The Deca presentation demonstrated how FO-WLP has grown from a niche solution as a single die package with a limited supply chain into a hyper-growth technology delivering the industry's highest interconnect density enabling multichip integration. With Moore's Law slowing due to economic challenges, system on a chip (SoC) designers are now partitioning monolithic silicon devices into multi-chip architectures that require tight die-to-die spacing and ultra-high density interconnect. Fan-out technology is now emerging as a key enabler of these future multichip SoC devices. However, cost, capability, yield and scale must all come together to enable mass market adoption. To address the cost and scale challenges, Deca sees the transition from wafer to panel level processing as a critical factor for future SoC architectures.