3-D Packaging Solution for High-performance Memory

摘要

The new generations of dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM) technologies are contributing to increased system performance significantly. Processing speed improvement, however, can be hampered by inefficiency in both package performance and module-level interconnect. Furthermore, these high-performance memory die have been designed with center bond pads rather than the peripheral bond format more common in earlier applications. The change in die layout, although challenging for traditional leadframe package technology, has proved ideal for array packaging.