Layer-by-Layer-Assembled Reduced Graphene Oxide/Gold Nanoparticle Hybrid Double-Floating-Gate Structure for Low-Voltage Flexible Flash Memory

摘要

Among the many possible device configurations of flash memory, field-effect-transistor (FET)-based memory with a floating-gate architecture is considered to be a promising candidate towards the ultimate goal of flash memory due to its single-transistor realization, non-destructive read-out, and compatibility with complementary metal oxide-semiconductor (CMOS) devices. Floating-gate FET memory with metal nanoparticles (NPs) embedded in the gate dielectric is a way to replace planar floating gates to meet the requirements of fast data access and high density for the next generation of flash memory.