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A New Opportunity for 2D van der Waals Heterostructures: Making Steep-Slope Transistors

机译:二维范德华异质结构的新机遇:制造陡坡晶体管

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The use of a foreign metallic cold source (CS) has recently been proposed as a promising approach toward the steep-slope field-effect-transistor (FET). In addition to the selection of source material with desired density of states-energy relation (D(E)), engineering the source:channel interface for gate-tunable channel-barrier is crucial to CS-FETs. However, conventional metal:semiconductor (MS) interfaces generally suffer from strong Fermi-level pinning due to the inevitable chemical disorder and defect-induced gap states, precluding the gate tunability of the barriers. By comprehensive materials and device modeling at the atomic scale, it is reported that 2D van der Waals (vdW) MS interfaces, with their atomic sharpness and cleanness, can be considered as general ingredients for CS-FETs. As test cases, InSe-based n-type FETs are studied. It is found that graphene can be spontaneously p-type doped along with slightly opened bandgap around the Dirac-point by interfacing with InSe, resulting in superexponentially decaying hot carrier density with increasing n-type channel-barrier. Moreover, the D(E) relations suggest that 2D transition-metal dichalcogenides and 2D transition-metal carbides are a rich library of CS materials. Graphene, Cd3C2, T-VTe2, H-VTe2, and H-TaTe2 CSs lead to subthreshold swing below 60 mV dec(-1). This work broadens the application potentials of 2D vdW MS heterostructures and serves as a springboard for more studies on low-power electronics based on 2D materials.
机译:最近,已提出使用外来金属冷源(CS)作为解决陡坡场效应晶体管(FET)的有前途的方法。除了选择具有所需状态-能量关系密度(D(E))的源材料以外,设计用于栅极可调沟道势垒的source:channel接口对于CS-FET也至关重要。然而,由于不可避免的化学无序和缺陷引起的间隙状态,常规的金属:半导体(MS)界面通常遭受强费米能级钉扎,从而排除了栅的栅极可调性。通过在原子尺度上进行全面的材料和器件建模,据报道,二维Van der Waals(vdW)MS接口及其原子的清晰度和清洁度可被视为CS-FET的常规成分。作为测试案例,研究了基于InSe的n型FET。发现通过与InSe介面,石墨烯可以自发地被p型掺杂,并且在Dirac点附近具有轻微开放的带隙,从而随着n型沟道势垒的增加,热载流子密度超指数衰减。此外,D(E)关系表明2D过渡金属二卤化物和2D过渡金属碳化物是CS材料的丰富库。石墨烯,Cd3C2,T-VTe2,H-VTe2和H-TaTe2 CS导致亚阈值摆幅低于60 mV dec(-1)。这项工作拓宽了2D vdW MS异质结构的应用潜力,并为基于2D材料的低功耗电子学的更多研究提供了跳板。

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