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Agile Blocker and Clock Jitter Tolerant Low-Power Frequency Selective Receiver with Energy Harvesting Capability

机译:具有能量收集功能的敏捷的阻滞器和时钟抖动容限低功率频率选择接收器

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摘要

In this article, a novel tunable, blocker and clock jitter tolerant, low power, quadrature phase shift frequency selective (QPS-FS) receiver with energy harvesting capability is proposed. The receiver’s design embraces and integrates (i) the baseband to radio frequency (RF) impedance translation concept to improve selectivity over that of conventional homodyne receiver topologies and (ii) broadband quadrature phase shift circuitry in the RF path to remove an active multi-phase clock generation circuit in passive mixer (PM) receivers. The use of a single local oscillator clock signal with a passive clock division network improves the receiver’s robustness against clock jitter and reduces the source clock frequency by a factor of N, compared to PM receivers using N switches (N≥4). As a consequence, the frequency coverage of the QPS-FS receiver is improved by a factor of N, given a clock source of maximum frequency; and, the power consumption of the whole receiver system can eventually be reduced. The tunable QPS-FS receiver separates the wanted RF band signal from the unwanted blockers/interferers. The desired RF signal is frequency down-converted to baseband, while the undesired blocker/interferer signals are reflected by the receiver, collected and could be energy recycled using an auxiliary energy harvesting device.
机译:在本文中,提出了一种具有能量收集功能的新型可调谐,具有阻止阻塞和时钟抖动的,低功耗,正交相移频率选择(QPS-FS)接收器。接收器的设计包含和集成(i)基带到射频(RF)阻抗转换概念,以提高对传统零差接收器拓扑结构的选择性,以及(ii)RF路径中的宽带正交相移电路,以去除有源多相无源混频器(PM)接收器中的时钟生成电路。与使用N个开关(N≥4)的PM接收器相比,将单个本地振荡器时钟信号与无源时钟分频网络一起使用可提高接收器的抗时钟抖动能力,并将源时钟频率降低N倍。结果,给定最大频率的时钟源,QPS-FS接收机的频率覆盖范围提高了N倍。并且,最终可以降低整个接收器系统的功耗。可调QPS-FS接收机将所需的RF频段信号与不需要的阻塞器/干扰器分开。所需的RF信号被频率下变频到基带,而不需要的阻止器/干扰器信号被接收器反射,收集并可以使用辅助能量收集设备进行能量回收。

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