基于FPGA的多cell腔的场平坦度控制

摘要

Background:The most important processing is division in the algorithm for the field flatness controller on multi-cell cavity. The algorithm in conventional integer division uses multiple subtraction and shift methods to achieve the operation. A lot of clocks are consumed in the subtraction process, and the cycles consuming is not fixed on each cycle of the division.Purpose:This study aims to design a circular unrecoverable divider based on FPGA (Field-Programmable Gate Array). Methods:Improvement is taken for meliorating the program structure and optimizing the time sequences to achieve speedup of the division and same clock cycle for each conventional division. This algorithm is implemented on FPGA chip using QuartusII, simulated and verified by ModelSim toolkits.Results:The stability of field flatness is less than ±1.3% and 35 cycles for each algorithm when it applied in the controller of DLLRF (Digital Low Level Radio Frequency) for the booster of Shanghai Synchrotron Radiation Facility (SSRF). Conclusion:Control of field flatness based on FPGA for multi-cell cavity satisfies all functional requirements, overperforms the design expectations.%在多cell腔的场平坦度控制处理中,最重要的算法为除法运算,而传统整数除法算法采用多次相减和移位的方法来实现,其算法存在以下缺点:相减运算消耗大量时钟即"吃时钟"、每完成一次算法所需时钟周期不固定以及此算法在实际工程中不能有效工作.针对传统整数除法器的弊端,提出一种基于现场可编程门阵列(Field-Programmable Gate Array,FPGA)的循环型不可恢复除法器.设计的循环型不可恢复除法器通过改善程序结构和优化时序,实现除法运算速度的提高和固定运算所需时钟周期的目的.此算法通过QuartusII编译和综合,以及仿真工具ModelSim的仿真验证,达到预期功能效果,同时在上海光源增强器高频数字低电平控制器中被采用,实现场平坦度稳定度在±1.3%以内,完成每次运算所需35个时钟周期,优于设计指标.