D-BL AST基带系统的FPGA实现研究

摘要

设计了适合于现场可编程门阵列实现的多输入多输出系统的对角分层空时码编译码算法。采用Verilog硬件描述语言在Xilinx Virtex4-VC4VSX55现场可编程门阵列开发板上实现了3×3对角分层空时编码基带处理系统。通过现场可编程门阵列仿真评估了采用迫零串行干扰抵消和最小均方误差串行干扰抵消检测算法时3×3对角分层空时编码基带系统的误码率性能。仿真分析和实验表明了现场可编程门阵列对角分层空时编码基带处理系统设计的正确性和高效性。同时，还论证了在同样条件下对角分层空时编码系统的性能优于垂直分层空时编码系统。%A MIMO D-BLAST codec algorithm iftted for FPGA implementation was designed. A 3×3 MIMO D-BLAST base-band processing system on the Xilinx Virtex4-VC4VSX55 test-bed was developed based on Verilog hardware description language. The BER performance of the 3×3 D-BLAST was simulated by FPGA implementation where two detection algorithms, ZF-SIC and MMSE-SIC, were adopted respectively. Simulation analysis and experimental results show the correctness and efifciency of the FPGA D-BLAST base-band processing system. It also shows that the BER performance of D-BLAST is better than V-BLAST under the same condition.