With the rapid increasing of the single-chip integration level, hardware verification plays a more important role during the system design process than before. The module-level verification executed by designers is no longer able to ensure the success rate of tape-out. A variety of effective and advanced verification methodologies and tools are developed to assist designers find and locate the design flaws as early as possible. Under the guidance of the Verification Methodology Manual (VMM), this paper presents a layered verification environment to co-simulate both the RTL description and the reference model of WTB controller based on the IEC61375 standards. Taking advantages of the reusable VMM library, randomized function and assertion-based verification, we construct an efficient, reusable verification platform to improve verification efficiency and test coverage. The practice results show that the application of this approach can efficiently reduce the verification effort and the developing time of verification environment, as well as improving the quality of verifying.%随着单芯片集成度的迅速提高,硬件验证在系统设计中占有越来越重要的地位.仅由设计者完成的模块级验证已经不能够保障流片成功率,需要在验证方法学指导下采用多种先进有效的验证技术和工具,帮助设计者尽可能早地发现和修改设计缺陷.本文详细介绍了在验证方法学VMM指导下,基于IEC61375-1标准的规定,设计分层次的验证环境,对绞线式列车总线控制器进行RTL和参考模型联合仿真的功能验证技术.通过可重用VMM库和随机化函数及基于断言的验证方法,编写高效、可重用的验证平台,以提高验证效率和覆盖率.实验表明,采用覆盖率导向的验证方法可有效地减少验证工作量和验证时间,提高验证质量.
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