一种高速开关电容动态锁存比较器分析与设计

摘要

A high speed switched capacitor dynamic comparator circuit in CMOS technology is presented. The comparator includes a switched capacitor sampling stage and a dynamic latched comparator.The input voltage range is improved by applying a switched capacitor sampling stage in the input stage.The speed of the dynamic latch is improved by employing two cross-coupled latch and other feedback circuits.The comparator is designed and simulated in a 0.18 la m 1.8V CMOS technology and the result shows that it meets the requirement of a 200 MSPS high resolution pipelined ADC.%设计了一种基于CMOS工艺的开关电容动态锁存比较器。该比较器包含一个共模不敏感全差分开关电容采样级和一级动态锁存比较器。开关电容采样级验证了比较器的输入共模范围，动态锁存器采用两个正反馈锁存器和额外的反馈环路提高了锁存的速度。基于0．18μm1．8VCMOS工艺进行了版图设计和后仿真，结果表明该比较器可以应用于200MSPS高精度流水线模数转换器。