片上网络的SystemC建模研究

摘要

In order to satisfy the requirement of hw/sw co-design and speedup of simulation,we use the modeling approach of SystemC language and study the architecture of network on a chip.The modeling approach for network on a chip is designed,and the design of mesh model is developed in this paper.The model can use the same testbench at system level and register transfer level,and it has a good simulation speed.The results show that the modeling approach achieves the design requirement.%为了实现软硬件协同设计和提高仿真速度的需求,采用SystemC语言的建模方法,通过对片上网络体系结构的研究,提出了一种片上网络的建模方案,并对一个mesh结构完成了SystemC的建模设计.该模型可在系统级和寄存器传输级上使用同一个测试平台,且具有仿真速度快的特点,达到了设计要求.