一种RapidIO IP核的设计与验证

摘要

The RapidIO bus as one of the representatives of the third generation bus,is the best choice of the interconnection between pro-cessors. But in the domestic,the study of RapidIO bus is just begun,and the RapidIO IP is bought from outland mostly. Based on the Ra-pidIO V1. 3 protocol,describe a design and implementation method for the RapidIO bus,and has carried on the comprehensive test in vir-tual platform and FPGA platform. The simulation result shows that,this design meets the RapidIO V1. 3 protocol,and is simple to imple-ment,has good reusability,and can be easily used in the design of FPGA and chip as RapidIO interface.%RapidIO总线是第三代总线的代表，是处理器之间实现互联的最佳选择。但国内对于此技术的研究尚处于起步阶段，使用者也多以购买国外成熟IP为主。文中基于RapidIO V1.3协议，介绍了一种RapidIO总线的设计和实现方法，之后对其进行了全面的虚拟平台测试和FPGA平台测试。测试结果表明，该RapidIO总线符合RapidIO V1.3协议，且设计实现方式简单，复用性好，可以作为RapidIO接口方便地应用于FPGA和芯片设计中。