Brent-Luk脉动阵列的一种仿真方法

摘要

Considering that the logic resource requirement of a large Brent-Luk (BL) eigen decomposition (EVD) systolic array is too high, a simulation method for BL array is proposed.This method uses a small simulation array to simulate a large BL array so that logic resource requirement can be reduced.The architecture of simulation array is similar to BL array, the interconnections among processing elements (PE) are independent of the scale of BL array, and the data interchanging among PEs is simple.Furthermore, acceleration of the simulation array can be carried out when the number of logic resources is limited.Performance analysis shows that this simulation array can simulate BL array with high efficiency.%在阵列算法提高处理速度问题的研究中,针对实现大规模Brent-Luk(BL)特征值分解脉动阵列需要的逻辑资源过多的问题,提出了阵列的一种仿真方法.使用较小的阵列仿真大规模BL阵列的功能从而节省逻辑资源.仿真阵列与BL阵列的结构相似,处理单元间的互连与原BL阵列的规模无关,而且处理单元间的数据交换简单,减少了数据交换,在逻辑资源限定的情况下,可实现仿真阵列的加速,并进行仿真计算.结果表明,仿真方法可高效地实现BL阵列的处理速度.