FPGA实际可用性评估与发展趋势分析

摘要

This paper introduces the development of Field Programmable Gate Array(FPGA), and evaluates the usability of FPGA devices which include the use of reconfigurable logic, Block RAM(BRAM), I/O resources, Digital Signal Processor(DSP) hard core, the selection of CPU soft core/hard core and the usable clock frequencies. It predicts future trend in the ever quest for high performance FPGA. It suggests not using slice resource more than 85％, selecting better supported tool company for soft/hard core and let all I/O signal buffered by registers.%根据现场可编程门阵列(FPGA)的发展现状,对FPGA器件的实际可用性进行评估,从可重构逻辑的利用、CPU软核/硬核的选择、内部块缓存的利用、输入/输出资源的利用、数字信号处理器固核的利用及时钟频率的可用范围进行研究,并给出FPGA的发展趋势.理论分析证明,Slice的利用率不宜高于85%,应选择有良好工具支持的软硬核厂商,并且所有的I/O信号须经过寄存器处理.