一种静态LoC关键性预测器设计

摘要

针对不同分簇超标量处理器结构下SPEC2000程序中指令关键可能性(LoC)的特性,提出一种静态LoC关键性预测器的设计方法.对指令LoC进行研究,根据其结构无关性和动态不变性,设计预测器.仿真结果表明,在对1×8分簇超标量处理器使用该设计时,程序的每周期指令数平均提升5.3％,性能优于动态LoC预测器.%Aiming at instruction Likelihood of Criticality(LoC) of SPEC2000 programs under different clustered superscalar processor architectures, this paper proposes a design of static LoC key predictor. It discusses the instruction LoC, and finds that it has some characteristics, such as architecture-independent and dynamic-invariable. This paper uses this characteristics above to design the predictor. Simulation results show that when 1×8 cluster super-scalar processor uses the design, the program Instruction per Clock(IPC) average increases by 5.3%, and the performance is better than the dynamic LoC predictors.