微处理器中完成一条有符号除法指令需要6个~38个周期。跳过符号处理直接用补码参与运算,可以节省符号处理的3个周期,从而提高除法器性能。为此,提出补码不恢复除法,将其运用于整数除法并给出算法证明,研究商的修正问题并给出解决方案。实验结果表明,该除法器在TSMC 130 nm工艺下的面积为12687μm2,完成一条有32位符号整数除法只需要2个~34个周期,相当于仅以多16%面积的硬件代价提升35%的有符号除法性能。%Signed integer division instruction takes 6~38 cycles to complete in general micro-processors. By using the original operands for division without abs and negation process,3 cycles of latency can be reduced which will effectively improve the division performance of processor. This paper focuses on complement no-restoring division and its application, as well as proof on integer division. This paper does a research in quotient correction and its reasonable solution and also implements the division device. Experimental result shows that the device is only 12 687μm2 in TSMC 130 nm process and can complete a 32 bit signed integer division in only 2~34 cycles,which means a performance improvement of 35% at a cost of only extra 16% area.
展开▼
