基于FPGA的通用型FIR数字滤波器的研究与设计

摘要

FIR digital filter is realized based on adders and multipliers. By delaying the multiplication accumulation of the inputted signal and the fixed tap coefficients, the filter results are obtained. The filter coefficient is known. When a fixed order number coefficient value is not fixed, we need to multiply the filter coefficients through external input with the input signal. Research on universal type of FIR digital filter is based on traditional serial FIR digital filter structure transformation, using Verilog HDL language in quartus and Modelsim software for design and simulation. The results show that the design of general FIR digital filter based on FPGA is feasible.%FIR 数字滤波器的实现是基于加法器和乘法器，通过延迟将输入信号与固定的抽头系数相乘累加得到滤波结果，其中滤波系数是已知的数值，当我们需要一个固定阶数系数的值不固定时，我们就需要将滤波的系数通过外部输入的方式再与输入信号相乘。对于 FIR数字滤波器的通用型的研究是基于传统的串行 FIR数字滤波器的结构进行改造，使用VerilogHDL语言在Quartus II和Modelsim软件里面进行设计和仿真。结果表明基于FPGA的通用FIR数字滤波器的设计是可行的。