具有秒脉冲接收功能的数据通讯模块设计

摘要

Describes a solution using the CPLD receives PPS, dual-port RAM address decoding and CPCI local bus communication hardware design, and gives the CPCI bus interface chip register configuration.%描述了一种使用CPLD解决秒脉冲接收、双端口RAM地址译码和CPCI局部总线通信的硬件设计方案,并给出了CPCI总线接口芯片的寄存器配置.