基于硬件描述语言的IPv6报文解析器设计

摘要

This paper present a implementations method of a IPv6 analyzer based on Verilog HDL language,which is integrated in IPv6 network coprocessor extensively, and analyzes the fuction of each module.The HDL module is coded by Verilog language,simulated and synthesized by EDA tools.%本文针对IPv6网络协处理器中应用普遍的IPv6解析器，提出一种解析器的硬件实现方法，分析了各个模块的功能和实现方式。并用硬件描述语言verilog搭建HDL模型，进行了仿真和逻辑综合。同时使用相关的EDA工具加以验证。