基于FPGA的高帧频面阵CCD驱动控制设计

摘要

According to the requirement of driving the area array CCD KAI -1020 in high frame rate mode, using FPCA as control unit and timing generator,completed the hardware and software design of CCD worked in high frame rate mode. Simulated and validated the correctness of driving timing, accomplished the debugging and experimentation of hardware. Hie imaging experiments show the design meets the diversified driving control function of CCD KAI-1020 worked in dual-port output mode, the image resolution is 1 000(H)?000(V), frame rate is 48 f/s.%针对面阵CCD KAI- 1020在高帧频工作模式下的驱动要求,以FPGA作为控制单元及时序发生器,完成CCD高帧频工作模式下的硬件及软件设计,仿真验证了驱动时序的正确性,完成了硬件电路的调试与试验.成像实验表明,该设计满足了CCD KAI- 1020在双端口输出模式下成像的各种驱动控制功能,图像分辨率为1000×1000,帧频达到48 f/s.