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Toward understanding the electrical properties of metal/semiconductor Schottky contacts: The effects of barrier inhomogeneities and geometry in bulk and nanoscale structures.

机译:理解金属/半导体肖特基接触的电性能:块体和纳米级结构中势垒不均匀性和几何形状的影响。

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摘要

The work presented in this thesis comprises of two parts. Part I deals with Schottky contacts to the wide bandgap (WBG) semiconductors SiC, GaN and ZnO. These semiconductors offer great promise for a wide variety of electronic and optoelectronic applications. Schottky barriers to WBG semiconductors are attractive in particular for high temperature/high power diodes, photodetectors, and gas sensors. However, the Schottky barriers exhibit non-ideal behavior, due in part to inhomogeneities originating from immature crystal growth and device processing technologies. Apart from being a versatile electronic component, the Schottky diode is a valuable test structure. The Schottky contact is routinely used to probe substrate and epilayer quality by different electrical characterization techniques.;It is well established that the current-voltage-temperature ( I-V-T) characteristics of Schottky contacts are routinely affected by the presence of barrier height inhomogeneities (BHI). Consequently, Schottky diode parameters such as the Schottky barrier height and the Richardson constant extracted using the I-V-T measurements can deviate from their actual values. The effects of BHI on the extracted Schottky barrier height have been studied in the literature. However, the effects of BHI on the Richardson constant have not been thoroughly explored and are the focus of the first part of this thesis. Based on the inhomogeneous Schottky barrier model provided by Tung, a new method for the extraction of the Richardson constant is developed. The new method is applied to the Richardson constant determination of n-type ZnO and GaN. Excellent agreement with the theoretical value is obtained in both cases.;The advent of the nanoelectronics era has resulted in the Schottky contact evolving from the relatively simple, planar structure into a more complex structure. Compared to bulk Schottky contacts, the Schottky barrier properties are expected to be widely different at the nanoscale. For example, the I-V characteristics of nanoscale Schottky contacts are affected by the contact size and geometry. Due to the increased surface-to-volume ratio, the conduction properties of nanoscale Schottky contacts are also influenced by surface conditions such as surface charge and traps. Depending on contact size, geometry and surface conditions, an enhanced tunneling current contribution can be expected, further distorting the I-V characteristics from the simple thermionic emission model. Determination of the true Schottky barrier height in nanoscale contacts to semiconductor nanowires is important from both technological and fundamental scientific perspectives. In the second part of this thesis, we employ a simulation-based approach to study the conduction properties of an axial Schottky nanocontact to a surround-gate nanowire. A systematic study of the effects of surface charge on the I-V characteristics of the axial nano Schottky/nanowire system is undertaken. Based on the study, a method is proposed to extract the true Schottky barrier height from the I-V characteristics. The proposed method can serve as a valuable aid for interpreting experimental I-V data and can facilitate exploration of size effects on the Schottky barrier formation at the nanoscale.
机译:本文提出的工作包括两个部分。第一部分介绍了与宽带隙(WBG)半导体SiC,GaN和ZnO的肖特基接触。这些半导体为广泛的电子和光电应用提供了广阔的前景。 WBG半导体的肖特基势垒特别适合高温/高功率二极管,光电探测器和气体传感器。然而,肖特基势垒表现出不理想的行为,部分原因是由于未成熟的晶体生长和器件加工技术引起的不均匀性。肖特基二极管除了是通用的电子元件外,还是一种有价值的测试结构。肖特基触点通常通过不同的电特性技术用于探测衬底和外延层的质量;众所周知,肖特基触点的电流-电压-温度(IVT)特性通常会受到势垒高度不均匀性(BHI)的影响。因此,使用I-V-T测量结果提取的肖特基二极管参数(例如肖特基势垒高度和Richardson常数)可能会偏离其实际值。在文献中已经研究了BHI对提取的肖特基势垒高度的影响。但是,BHI对Richardson常数的影响尚未得到充分探讨,并且是本论文第一部分的重点。基于Tung提供的非均匀肖特基势垒模型,开发了一种新的理查森常数提取方法。该新方法应用于n型ZnO和GaN的Richardson常数测定。在这两种情况下都获得了与理论值的极佳吻合。纳米电子时代的到来使肖特基接触从相对简单的平面结构演变为更复杂的结构。与块状肖特基接触相比,肖特基势垒性能在纳米级上有望有很大的不同。例如,纳米级肖特基接触的I-V特性受接触尺寸和几何形状的影响。由于增加的表面体积比,纳米级肖特基接触的导电性能也受到表面条件(例如表面电荷和陷阱)的影响。根据接触尺寸,几何形状和表面条件,可以预期会增加隧穿电流,从而进一步使I-V特性偏离简单的热电子发射模型。从技术和基础科学的角度来看,确定与半导体纳米线的纳米级接触中的真正肖特基势垒高度都很重要。在本文的第二部分,我们采用基于仿真的方法来研究轴向肖特基纳米接触环栅纳米线的导电特性。对表面电荷对轴向纳米肖特基/纳米线系统的I-V特性的影响进行了系统的研究。在此基础上,提出了一种从IV特性中提取真实肖特基势垒高度的方法。所提出的方法可以作为解释实验I-V数据的有价值的帮助,并且可以促进纳米尺度上对肖特基势垒形成的尺寸效应的探索。

著录项

  • 作者

    Sarpatwari, Karthik.;

  • 作者单位

    The Pennsylvania State University.;

  • 授予单位 The Pennsylvania State University.;
  • 学科 Engineering Electronics and Electrical.;Engineering Materials Science.
  • 学位 Ph.D.
  • 年度 2009
  • 页码 177 p.
  • 总页数 177
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

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