Hardware acceleration on IBM cell broadband engine for simulation of coupled interconnects using waveform relaxation and transverse partitioning.

摘要

Over the past few years, the trend in microprocessor design has shifted from increasing the clock frequencies to multi-core designs that embed multiple processing cores on the same chip. This has meant that we can no longer rely on increasing clock frequencies in order to improve the performance of electronic design automation (EDA) tools. In fact, for these tools to take advantage of modern advances in microprocessor design they must be adapted to take advantage of parallel computing architectures. In this thesis we parallelize and implement an algorithm on the IBM Cell Broadband Engine (Cell BE), which is based on the techniques of waveform relaxation and transverse partitioning to efficiently simulate large coupled interconnect circuits at high speed. Several strategies are used in the Cell BE programs to achieve high performance. The Cell BE processor achieves the best performance with a speed-up of 10x when the number of transmission lines is a multiple of the maximum number of Synergistic Processor Elements (SPEs) that are running concurrently.