Design of 3.3V digital standard cells libraries for LEON3.

摘要

Scope and Method of Study. The scope of the research work was to develop 3.3V digital standard cell library for LEON3 operable at 200°C using Peregrine 0.5mum process. The dimension of the transistors was determined based on the work of Singravelan Vishwanathan. Layout and abstracted view were generated for the library. In total we have 259 cells. The cell library is characterized for timing and power data. The characterized data of the cells are documented in html format along with the lib format. The lib format file is used for synthesis and place and route.;Findings and Conclusions. The dimension of the minimum size transistor used IX NMOS is length 1im and width 1.4mum and dimension of IX PMOS is length 0.6mum and width 1.6mum and the drive strength was set using buffer. The cell library was completed, characterized and abstracted. The cells were simulated across temperature range of -25°C to 200°C and across a supply voltage range of 3V to 3.6V. In the process of characterization and abstraction we gained a good understanding of the characterization and abstraction tool. The layout was validated by checking the DRC and LVS and we were finally able to complete the place and route of LEON3 within a area of 6.5mm by 6.5mm.