An integrated random bit generator for applications in cryptography.

摘要

The design of a random bit generator analog IC suitable for integration with hardware cryptographic systems is presented. Certain applications in cryptography require the production of an unpredictable and unbiased stream of binary data derived from a fundamental noise mechanism. The amplification of noise to produce a random bitstream in the presence of typical non-random IC disturbances presents a challenging analog IC design problem. Background material in hardware random bit generator design is presented, including a discussion of randomness for random bit generators and a literature review of prevalent random bit generator methods. New methods to simulate for randomness are developed and an efficient simulation model which tracks the effects of key circuit parameters on the randomness of common and original random bit generator implementations is presented. The detailed design of a high performance random bit generator system comprised of familiar analog sub-circuits is discussed. A prototype random bit generator IC was constructed and tested to be functional for bit rates up to 1.4 MHz. Sequences generated by the experimental system passed many standard randomness tests even when the system was exposed to non-random influences such as power supply noise and substrate signal coupling. The system occupied a total chip area of 1.5 mm