An optimization-based approach for cost-effective embedded DSP system design.

摘要

Front-end embedded digital signal processing (DSP) system design typically involves less than 10% of the total prototyping time and cost, but accounts for over 80% of a product's life-cycle cost. Yet designers currently rely upon experience and ad hoc, manual techniques to make these early, crucial design decisions. These hand-crafted techniques, which were sufficient to design small, low-performance systems in the past, are inadequate for the design of today's large-scale, high-performance embedded systems. Such techniques enable the exploration of only a few potential designs within an enormous design space, thus leading to low design quality and potential customer dissatisfaction. To improve the situation, an automated, systematic design approach that leverages systems engineering: economic factors, application requirements, and state-of-the-art hardware/software (HW/SW) technology when choosing key architectural attributes is needed.; This thesis presents a novel automated preliminary architecture design approach for embedded DSP systems. Given a DSP application data flow graph, system-level economic cost parameters, algorithm performance benchmark timings, and physical parameters, the objective of this thesis is to develop a systematic methodology for choosing key HW/SW architectural attributes in a way that optimizes cost-related objective functions while satisfying stringent system-level performance and form factor (such as size, power, and weight) constraints. Aimed at commercial off-the-shelf (COTS)-based embedded DSP systems, our approach uses parametric cost and development time estimation models, which reliably estimate product development, maintenance, and time-to-market costs, to drive the design optimization process. The model the architecture selection and partitioning process using mathematical programming formulations. This optimization-based approach automatically synthesizes HW/SW architectural candidates, which are subsequently verified and refined using an efficient library-based cosimulation and coverification approach, known as VHDL performance modeling.; To validate the feasibility and efficiency of this approach, we present a detailed case study of a polarimetric synthetic aperture radar (SAR) system used to form images on board an aircraft. The substantial throughput and memory requirements associated with the SAR application make it a suitable application vehicle for use in benchmarking our optimization-based design approach. We perform a detailed cost analysis to demonstrate the influence of software costs, time-to-market costs, and hardware production costs on overall system costs. To quantify the case study results, we provide estimates of improvements in development time and life-cycle cost as compared with traditional approaches over a range of production volumes and time-to-market constraints.