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A fully integrated transmitter for on-wafer wireless testing.

机译:完全集成的发射机,用于晶片上无线测试。

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摘要

A fully integrated transmitter with embedded on-chip antenna for on-wafer wireless testing (OWT) is presented. The goal of OWT is to replace high-speed I/O pins in conventional probe cards with wireless links during IC manufacturing test. In this dissertation, key enabling technologies for OWT are investigated. First, an accurate on-chip antenna characterization method is developed to enable the assessment of antenna gain, which is essential for establishing the wireless link budget between a wafer and a tester. Second, an image rejection transmitter with on-chip antenna is designed for sending signals wirelessly from a wafer to a tester. Finally, the design of an antenna switch that permits on-chip antennas to be shared among multiple transmitters and receivers is presented.;Increasing interest in the integration of antennas on chip is fueled by a number of emerging applications ranging from miniature RFID tags to millimeter-wave radios. On-chip antennas have been demonstrated with promising performance for short-range (10 m) communications; however, an accurate characterization method to determine the on-chip antenna gain and the radiation pattern is still lacking. A novel on-chip antenna characterization method that achieves improved accuracy and sensitivity is developed. The method utilizes a two-step technique using discrete antennas for calibration and to characterize on-chip antenna. Based on the proposed method, on-chip antenna gains over a wide frequency bandwidth are measured. The measured data showed excellent repeatability. Using a folded dipole as a test vehicle, we confirm that a typical on-chip antenna can support OWT with good sensitivity.;To demonstrate wireless testing from a wafer to a tester, a fully integrated image rejection transmitter is employed. By exploiting the sensitivity of the image rejection ratio (IRR) to I and Q path mismatches, the RF and image signals are wirelessly transmitted through the on-chip antenna. The gain of a loop antenna and dipole antenna are compared by using two different transmitter designs. The wirelessly measured IRR results showed consistency with results obtained by direct probing. The proposed IR transmitter provides two distinctive functions. It can replace the I/O pins during testing and can act as a process variation monitoring circuit. Monte Carlo simulations are used to aid the analysis of the sources of amplitude and phase mismatches in the IR transmitter. To reduce the area requirement for implementing the OWT, it is desirable to minimize the number of on-chip antennas due to their large dimensions. On-chip antenna switches enable the antennas to be shared by several transmitters and receivers. Trade-offs and design guidelines for implementing a CMOS antenna switch to achieve high linearity at frequencies above 20 GHz are investigated. The circuit techniques to facilitate performance optimization among linearity, isolation, switching speed, insertion loss and silicon area are studied in detail. A prototype of a 24-GHz transmit/receive switch is designed in a 90 nm CMOS process. It achieved the highest linearity in the smallest footprint among previously published CMOS switch designs operating above 20 GHz.
机译:提出了一种用于晶片上无线测试(OWT)的,具有嵌入式片上天线的完全集成的发射机。 OWT的目标是在IC制造测试期间用无线链路替换传统探针卡中的高速I / O引脚。本文研究了OWT的关键实现技术。首先,开发了一种精确的片上天线表征方法,以实现天线增益的评估,这对于在晶圆和测试仪之间建立无线链路预算至关重要。其次,带有片上天线的图像抑制发射器被设计用于将信号从晶圆无线发送到测试仪。最后,提出了一种允许在多个发射器和接收器之间共享片上天线的天线开关的设计。;从微型RFID标签到毫米级的许多新兴应用推动了人们对片上天线集成的兴趣日益增加。无线电。片上天线已被证明具有可用于短距离(<10 m)通信的性能。然而,仍然缺乏确定片上天线增益和辐射方向图的准确表征方法。开发了一种新颖的片上天线表征方法,该方法可实现更高的精度和灵敏度。该方法利用使用分立天线的两步技术进行校准并表征芯片上天线。基于所提出的方法,可以测量宽频率带宽上的片上天线增益。测量数据显示出极好的可重复性。使用折叠偶极子作为测试工具,我们确认典型的片上天线可以以良好的灵敏度支持OWT。为了演示从晶片到测试仪的无线测试,采用了完全集成的镜像抑制发射器。通过利用镜像抑制比(IRR)对I和Q路径失配的敏感性,RF和图像信号通过片上天线无线传输。通过使用两种不同的发射机设计比较了环形天线和偶极天线的增益。无线测量的IRR结果显示与通过直接探测获得的结果一致。提议的红外发射器具有两种独特的功能。它可以在测试期间替换I / O引脚,并可以用作过程变化监视电路。蒙特卡洛模拟用于帮助分析红外发射器中幅度和相位不匹配的来源。为了减小用于实现OWT的面积要求,由于其大尺寸,期望最小化片上天线的数量。片上天线开关使天线可以被多个发射器和接收器共享。研究了在20 GHz以上的频率下实现CMOS天线开关以实现高线性度的权衡和设计指南。详细研究了有助于线性度,隔离度,开关速度,插入损耗和硅面积之间性能优化的电路技术。采用90 nm CMOS工艺设计了24 GHz发送/接收开关的原型。在先前发布的工作于20 GHz以上的CMOS开关设计中,它以最小的占位面积实现了最高的线性度。

著录项

  • 作者

    Park, Pil Jae.;

  • 作者单位

    University of California, Santa Barbara.;

  • 授予单位 University of California, Santa Barbara.;
  • 学科 Engineering Electronics and Electrical.
  • 学位 Ph.D.
  • 年度 2009
  • 页码 136 p.
  • 总页数 136
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 无线电电子学、电信技术 ;
  • 关键词

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