Optimizing average-case performance in the technology mapping of asynchronous circuits.

摘要

This thesis presents a technology mapper that optimizes average-case performance of two asynchronous design styles: burst-mode control circuits and one-hot domino control circuits. The mapping procedure consists of two phases: decomposition and covering. Circuits are first decomposed into unmapped NAND2-INV networks which are then covered using a given library of gates. The specification of these circuits are preprocessed using stochastic techniques or architectural simulations to determine the input patterns of interest and their relative frequencies which guide the mapper to shorten the critical paths for common input patterns. More specifically, the mapper minimizes the weighted sum of circuit performance for all input patterns, thereby optimizing the mapped circuits for average-case performance. Our experimental results demonstrate that, with manageable run-times, our mapped circuits have significant higher average-case performance and smaller area than the comparable circuits mapped using a leading conventional mapping technique which minimizes worst-case delay.