Design techniques for high performance integrated frequency synthesizers for multi-standard wireless communication applications.

摘要

The growing importance of wireless media for voice and data communications is driving a need for higher integration in personal communications transceivers in order to achieve lower cost, smaller form factor, and lower power dissipation. One approach to this problem is to integrate the RF functionality in low-cost CMOS technology together with the baseband transceiver functions. This in turn requires integration of the frequency synthesizer with enough isolation from supply noise to allow the synthesizer to coexist with other on-chip transceiver circuitry and still meet the phase noise performance requirements of the application.;This research proposes a differential synthesizer for block-down-convert receivers that achieves improved levels of phase noise and supply rejection performance through the use of fully differential architecture and a wide-bandwidth PLL. Analytical relationships for such a system relating output phase noise to system design parameters and internal noise sources are developed. A prototype systems embodying the design principles, and also embodying new differential circuit configurations which minimize supply coupling is designed, laid out and fabricated. The performance of the prototype synthesizer as a stand alone device is evaluated. The synthesizer is embodied in a complete integrated radio system and the performance of the synthesizer in the complete radio system is also evaluated.