Modern chip design pushes the performance of a given technology to its limits, therefore it is necessary to find increasingly more accurate models for interconnect parasitics. The growing complexity of today's integrated systems, however, makes fast analysis crucial as well. Due to the wide range of applications of interconnect modeling in chip design, it is unreasonable to assume there is just one method which fits in all cases equally well.; Two new localized extraction techniques which ensure the stability of the interconnect parasitic model while allowing for fast and accurate analysis are introduced. We investigate hierarchical models which are able to represent detailed near field and global far field couplings with equal accuracy and efficiency. A novel approach for efficient extraction of on-chip inductance and capacitance is presented, combining the best features of previously existing hierarchical approaches in this field. Finally, we discuss methods for generating hierarchical equivalent circuit models for interconnect parasitic couplings for use in existing tools.; The various methods developed are applied to examples throughout the thesis.
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