Design and evaluation of high-performance routers.

摘要

In order to cope with the ever-increasing size of routing tables as well as the high-speed backbone links in the Internet, a hardware-based and a hardware-assisted high-performance router are investigated. The former approach considers the use of an SMT (simultaneous multithreading) processor in lieu of the conventional processor(s) in a high-speed router and evaluates quantitatively the potential gains resulting from this change. An SMT processor exploits the benefits of both ILP (instruction level parallelism) and TLP (thread level parallelism). It is suitable for the next generation routers, in which an increased number of functions are to be implemented, e.g., packet classification and differentiation for the quality of service purpose, rapid packet forwarding via multiple forwarding engines, and security.; The second approach proposes a hardware-assisted mechanism for fast packet forwarding, dubbed the cache-oriented multistage structure (COMS), which incorporates small fast cache memory in its constituent switching elements (SEs). COMS is a multistage-based interconnect. It connects line cards (LCs) and forwarding engines (FEs), and caches each lookup result (i.e., an IP address and its next hop interface number) in a series of SEs between the LC (where the lookup request originates) and the FE (which performs the lookup). It exhibits faster packet forwarding as the forwarding table size grows. It is ideally suitable for high-performance routers.