High purity frequency synthesizer design in CMOS.

摘要

This dissertation reports on a fully integrated low power, 900 MHz GSM synthesizer and GMSK modulator realized in 0.35 μm CMOS process. It uses a ΔΣ Fractional-N PLL architecture to combine the functionality of a modulator with that of a channel-select synthesizer. This architecture provides high signal purity, low power and fast settling. The total power consumption is 17 mW for the GMSK modulator mode and 12 mW for the synthesizer mode and meets all GSM specifications.; To achieve this performance, new topologies for voltage controlled oscillators are developed. This helped improve the understanding of the oscillator design problem and lead to a new design methodology for voltage controlled oscillators. A theoretical treatment of the seldomly analyzed varactor tuning and noise implications is also reported. Simple, yet accurate, expressions are arrived at to describe precisely the tuning action of the varactor and its impact of converting AM noise to FM noise in voltage controlled oscillators.