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High performance packet forwarding on parallel architectures.

机译:并行体系结构上的高性能数据包转发。

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摘要

Packet forwarding has long been a performance bottleneck in Internet infrastructure, including routers and switches. While the throughput requirements continue to grow, power dissipation has emerged as an additional critical concern. Also, as the Internet continues to constantly evolve, packet forwarding engines must be flexible in order to enable future innovations. Although ternary content addressable memories (TCAMs) have been widely used for packet forwarding, they have high power consumption and are inflexible for adapting to new addressing and routing protocols.;This thesis studies the use of low-power memory, such as static random access memory (SRAM) combined with application-specific integrated circuit (ASIC)/fieldprogrammable gate array (FPGA) technology, to develop high-throughput, power-efficient, and flexible algorithmic solutions for various packet forwarding problems, which include IP lookup, packet classification and flexible flow matching (such as OpenFlow).;We propose to map state-of-the-art packet forwarding algorithms onto SRAM-based parallel architectures. High throughput is achieved via pipelining and/or multi-processing. Several challenges for such algorithm-to-architecture mapping are addressed. Meanwhile, enabled by the customized architecture design, the algorithms are optimized to achieve memory and/or power/energy efficiency. (1) For IP lookup, we propose two mapping schemes to balance the memory distribution across the stages in a pipeline. In the case of multi-pipeline architectures, our schemes balance both the memory requirement and the traffic load among multiple pipelines. The intra-flow packet order is also preserved. (2) In addition to the power reduction achieved by replacing TCAMs with SRAMs, we propose data structure and architectural optimizations to further lower the power/energy consumption for SRAM-based pipelined IP lookup engines. (3) For packet classification, we propose a decision-tree-based, two-dimensional dual-pipeline architecture. Several optimization techniques are proposed for the state-of-the-art decision-tree-based algorithm. As a result, the memory requirement is almost linear with the number of rules in the forwarding table. (4) Considering OpenFlow as a representative of flexible flow matching, we develop a framework to partition a given table of flexible flow rules into multiple subsets, of which each is built into a depth-bounded decision tree. The partitioning scheme is carefully designed to reduce the overall memory requirement. We evaluate our solutions implemented on modern ASIC/FPGA and demonstrate their superior performance over the state-of-the-art with respect to throughput, memory requirement and power/energy consumption.
机译:长期以来,数据包转发一直是Internet基础结构(包括路由器和交换机)中的性能瓶颈。在吞吐量要求不断增长的同时,功耗也成为了另一个关键问题。另外,随着Internet的不断发展,分组转发引擎必须具有灵活性,才能实现未来的创新。尽管三态内容可寻址存储器(TCAM)已被广泛地用于数据包转发,但它们具有很高的功耗,并且不适应新的寻址和路由协议。本论文研究了低功率存储器的使用,例如静态随机访问。存储器(SRAM)与专用集成电路(ASIC)/现场可编程门阵列(FPGA)技术相结合,为各种数据包转发问题(包括IP查找,数据包分类)开发高吞吐量,高能效,灵活的算法解决方案我们建议将最新的数据包转发算法映射到基于SRAM的并行体系结构上。通过流水线和/或多处理可实现高吞吐量。解决了这种算法到体系结构映射的几个挑战。同时,通过定制的体系结构设计,对算法进行了优化,以实现内存和/或电源/能源效率。 (1)对于IP查找,我们提出了两种映射方案来平衡流水线中各个阶段的内存分配。在多管道体系结构的情况下,我们的方案在多个管道之间平衡了内存需求和流量负载。流内分组顺序也被保留。 (2)除了通过用SRAM代替TCAM来降低功耗外,我们还提出了数据结构和体系结构优化,以进一步降低基于SRAM的流水线IP查找引擎的功耗/能耗。 (3)对于数据包分类,我们提出了一种基于决策树的二维双流水线架构。针对基于最新决策树的算法,提出了几种优化技术。结果,内存需求几乎与转发表中规则的数量成线性关系。 (4)考虑将OpenFlow表示为灵活流匹配的代表,我们开发了一个框架,用于将给定的灵活流规则表划分为多个子集,每个子​​集都内置在深度限制的决策树中。精心设计了分区方案,以减少总体内存需求。我们评估了我们在现代ASIC / FPGA上实现的解决方案,并展示了它们在吞吐量,内存需求和功耗/能耗方面均优于最新技术。

著录项

  • 作者

    Jiang, Weirong.;

  • 作者单位

    University of Southern California.;

  • 授予单位 University of Southern California.;
  • 学科 Engineering Computer.
  • 学位 Ph.D.
  • 年度 2010
  • 页码 133 p.
  • 总页数 133
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

  • 入库时间 2022-08-17 11:36:46

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