Analytical model development for LC Parasitic estimation in power electronics circuits.

摘要

Technology trends in Power Electronics (PE) design continue to move toward board size reduction and increasing operating frequencies. However, as board sizes are reduced and operating frequencies increased, Electromagnetic Interference (EMI) increasingly becomes a real limiting issue. The inherent parasitic resistance, capacitance, and inductance present in PE Printed Circuit Board (PCB) traces has been identified as one of the main causes of EMI. As a result, PCB parasitics need to be estimated and minimized. This work presents the development of a fast and accurate PCB parasitic estimation tool, applicable to Power Electronics circuits. This tool uses a semi-lumped approach that divides each PCB trace into simpler segments where analytical equations can be directly applied to obtain the desired parasitic elements. The total parasitic estimate in a trace is computed from the contributions of all its sub-segments and their interactions. The speed advantage gained by this method created the opportunity of using it into automated PCB layout parasitic minimization methods.