Circuit and CAD Solutions for Optimal SRAM Design in Nanoscale CMOS.

摘要

Conventional SRAM design involves balancing trade-offs among several critical metrics---yield, power, performance and area. Worsening variation makes scaling the 6T bitcell difficult, especially due to the need to balance the trade-offs between various metrics. In particular, lowering the SRAM voltage for low-power, while maintaining functionality, is challenging. Several solutions have been proposed to ensure continued SRAM scaling at the process, circuit, and architectural levels. Exploring this vast design space to zero in on an optimal design thus becomes challenging. This dissertation makes the following contributions to ensure continued scaling of SRAM.;First, we present bitcells that use asymmetric sizing of the cross-coupled inverter to improve read stability. Further, these bitcells can use sizing as an effective knob to improve stability and to trade-off leakage power, read performance, writability, and area. An improvement in cell stability ensures scalability of SRAM to lower voltages for lower power, while maintaining acceptable levels of functional yield.;Second, due to the DC assumptions of conventional static metrics, they are either optimistic or pessimistic in predicting cell failure. The static metrics predict cell failure only by considering variation, while there are several other factors involved in the dynamics of a write operation that can cause failure. So, we define Dynamic write-limited VMIN for an SRAM that is based on TWL-CRIT, a dynamic writability metric. DWVMIN takes into account several other factors that can cause write failure and is a more accurate value of the lowest operating voltage for write-limited SRAMs.;Finally, the burgeoning SRAM design space has led to a designer productivity crisis. Thus, to improve productivity and enable a rapid and early exploration of the design space, we propose the Virtual Prototyping tool. For any technology, ViPro produces an optimal base-case SRAM prototype, metric trade-off curves, and breakdown among various components. The designer can then iteratively explore the design space to reach an optimal design. The Technology Agnostic Simulation Environment component of ViPro can be used as a stand-alone tool to port circuit analysis across technologies.