首页> 外文学位 >Design, fault studies, and performance analysis for nanomagnet logic PLAs and other nanomagnet logic architectures.
【24h】

Design, fault studies, and performance analysis for nanomagnet logic PLAs and other nanomagnet logic architectures.

机译:纳米磁铁逻辑PLA和其他纳米磁铁逻辑体系结构的设计,故障研究和性能分析。

获取原文
获取原文并翻译 | 示例

摘要

In order to continue the performance and scaling trends that we have come to expect from Moore's Law, many emergent computational models, devices, and technologies are actively being studied to either replace or augment CMOS technology. Nanomagnet Logic (NML) is one such alternative. NML is a device architecture that utilizes the magnetization of nano-scale magnets to perform logical operations. NML has been experimentally demonstrated and operates at room temperature.;We present an NML Programmable Logic Array (PLA) based on a previously proposed reprogrammable Quantum-dot Cellular Automata PLA design. We also discuss the fabrication and simulation validation of the circuit structures unique to the NML PLA. We present a fault model for NML PLAs, and provide an improved technique for mapping logic to the NML PLA. We present area, energy, and delay estimates for the NML PLA, compare the area of NML PLAs to other reprogrammable nanotechnologies, and analyze how architectural-level redundancy will affect performance and defect tolerance in NML PLAs.;Because the nanomagnets are non-volatile, as data flows through a circuit, it is inherently pipelined. This feature makes NML an excellent fit for systolic architectures, which could enable low-power, high-throughput systems that can address a variety of application-level tasks. When considering possible NML systolic systems, the underlying systolic clocking scheme affects both architectural design and performance. We explore these issues in the context of two NML designs for simplified convolution, both of which focus on different data flow patterns. We also study N-bit NML adders and multipliers in the context of high-throughput NML systems. We compare parallel and serial NML designs and compare NML to CMOS in terms of delay and energy. We also explore possible performance enhancement techniques for NML in an effort to make NML as low energy as possible.
机译:为了保持摩尔定律所期望的性能和扩展趋势,正在积极研究许多新兴的计算模型,设备和技术,以替代或增强CMOS技术。纳米磁铁逻辑(NML)就是这样一种选择。 NML是一种利用纳米级磁体磁化来执行逻辑操作的设备体系结构。 NML已通过实验证明并在室温下运行。我们基于先前提出的可重编程量子点元胞自动机PLA设计提出了NML可编程逻辑阵列(PLA)。我们还将讨论NML PLA特有的电路结构的制造和仿真验证。我们提出了NML PLA的故障模型,并提供了一种将逻辑映射到NML PLA的改进技术。我们提供了NML PLA的面积,能量和延迟估计值,将NML PLA的面积与其他可重新编程的纳米技术进行了比较,并分析了架构级冗余将如何影响NML PLA的性能和缺陷容忍度;因为纳米磁铁是非易失性的,当数据流经电路时,它本身就是流水线。此功能使NML非常适合脉动体系结构,这可以启用低功耗,高吞吐量的系统,以解决各种应用程序级任务。在考虑可能的NML心脏收缩系统时,基础的心脏收缩时钟方案会影响体系结构设计和性能。我们在两种用于简化卷积的NML设计的背景下探讨了这些问题,它们都专注于不同的数据流模式。我们还研究了高吞吐量NML系统中的N位NML加法器和乘法器。我们比较并行和串行NML设计,并就延迟和能量将NML与CMOS进行比较。我们还探索了NML可能的性能增强技术,以使NML尽可能低能耗。

著录项

  • 作者

    Crocker, Michael S.;

  • 作者单位

    University of Notre Dame.;

  • 授予单位 University of Notre Dame.;
  • 学科 Engineering Computer.
  • 学位 Ph.D.
  • 年度 2011
  • 页码 217 p.
  • 总页数 217
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

  • 入库时间 2022-08-17 11:45:14

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号