While enabling the integration of hundreds of millions of transistors on a chip, nanometer technologies exacerbate existing challenges such as the design productivity gap and the timing closure problem. Latency-insensitive design (LID) has been proposed as a correct-by-construction methodology to cope with these problems without requiring major changes to the traditional design flows that are based on the synchronous paradigm. LID helps designers (1) to handle the complexity of system-level design by simplifying the assembling of pre-designed cores and (2) to meet the target clock frequency by simplifying the pipelining of global interconnect wires. On the other hand, the application of LID may lead to a decrease of the system's data-processing throughput. In fact, for high-performance designs the original timing closure problem may translate into a throughput-closure problem. I present a collection of research contributions for the optimization and validation of latency-insensitive systems that are applicable at different stages of the design process. At the register-transfer level I propose new designs of the LID building blocks, i.e., shell interfaces and relay stations, that are based on a simplified latency-insensitive protocol as well as a new logic synthesis optimization technique that takes advantage of functional-independence conditions to increase the data-processing throughput. At the physical-design level I propose new throughput-driven partitioning and throughput-preserving merging algorithms incorporated in a new physical synthesis flow to improve the performance of a latency-insensitive system. The validation of the proposed contributions is performed through a combination of formal methods and experimental results, which include two designs of a system-on-chip with industrial nanometer technology processes.
展开▼
