C-RAM with a fault-tolerant reconfigurable one-dimensional, two-dimensional, three-dimensional communication network.

摘要

This thesis introduces a reconfigurable interconnection network for Computational RAM (C•RAM) that incorporates 1D, 2D and 3D communication between processing elements. The processing element mesh is designed to be a dynamically reconfigurable interconnection network with fault-tolerance extending into all three dimensions of the mesh. A novel memory bank architecture for C•RAM is also proposed that allows for computations and load/store operations to occur simultaneously.;The efficiency of operation for C•RAM is enhanced by the introduction of the dynamically reconfigurable interconnection network, since shifting can be performed more efficiently. The efficiency of C•RAM is also enhanced by the memory bank architecture, since computations are maximized by allowing computations to be performed in parallel with external memory access.