Timing driven IP block design methodology with emphasis on reusability.

摘要

The steady down-scaling of Complementary Metal Oxide Semiconductor (CMOS) device dimensions drives Application Specific Integrated Circuit (ASIC) designers to a situation where they find themselves able to fit a seemingly limitless number of transistors on a single die. As a result, integrated circuits have become more complex and the design cycle time becomes longer, increasing the time-to-market. Design for reuse seems to be one of the main solutions to reduce the gap between engineering productivity and the capacity/performance made possible by Deep Submicron (DSM) technology. Building a System-on-Chip (SoC) using reusable Intellectual Property (IP) blocks is widely accepted as the key to achieve fast and reliable implementation of embedded systems, and to satisfy market demands. IP blocks may vary from fixed architectures (hard IP blocks) to Register-Transfer level (RTL) code (soft IP blocks). Developing an IP block to a specific level of abstraction depends on the required predictability and flexibility, which are conflicting goals. The reusability of a design is expressed by the amount of predictability and flexibility it has, thus a new design methodology that promotes both of these attributes is in great demand.; In this thesis the outline for developing a new IP blocks design methodology was proposed. This methodology emphasizes on reusability by relying on technology independent techniques such as library-free mapping and symbolic layout. Using a library-free technique necessitates the development of technology-portable analytical models to characterize and optimize the cell's performance. Timing characterization and optimization were the main focus of this work. Therefore, new technology-portable transition time and delay models have been formulated. These models consider the CMOS inverters, as well as CMOS complex gates. Moreover, they account for DSM effects, input transition time, output loading and do not depend on fitting or extracted parameters. These models achieve very good accuracy compared with the BSIM3v3 model.; Also, during this work a new technique has been developed to size the transistors of logical path gates with the objective of minimizing path delay or optimizing the gate areas to attain a required time. Compared to the Synopsys's Design Complier, the developed technique reduces the area-delay product by 50% on average.