Design, implementation and testing of a hybrid algorithmic SigmaDelta A/D converter.

摘要

With the proliferation of miniaturized and autonomous sensors there has been an ever-increasing demand for reconfigurable analog-to-digital converter (ADC) architectures that can efficiently trade-off speed and resolution with its power consumption. This work describes design, implementation and testing of a dynamically reconfigurable ADC, which can be integrated as a smart front-end to low-power sensor. The ADC utilizes the principle of extended data conversion to achieve adaptation between a sigma-delta (SigmaDelta) and an algorithmic converter. Based on the input signal statistics, the adaptation can be directly parameterized and used for dynamic reconfigurability to achieve an optimum trade-off. A pseudo-differential ADC architecture has been implemented using switched-capacitor techniques and its functionality has been validated through extensive simulations. A prototype of the ADC has been fabricated using a standard 0.5mum CMOS process and has been tested to be fully functional. The ADC can achieve 8-bit in first-order SigmaDelta mode and 4-bit in algorithmic SigmaDelta mode and consumes only 8.6muW during operation.