A High-Rate, Low-Power, Hardware Architecture For Speed Recognition Using Finite State Transducers.

摘要

As an increasing amount of speech recognition is performed server-side in data centers, the efficiency of the processors used to perform speech recognition becomes increasingly important. To address this, we present a novel and highly efficient hardware architecture to perform speech decoding. Given our focus on efficiency, we explore an algorithm that trades higher memory requirements for less runtime computation through the use of Weighted Finite State Transducers. By developing our own software decoder to use as the baseline for our hardware architecture, we are able to customize every level of our design. We then explore a wide range of serial and parallel hardware architectures by running cycle-accurate, RTL-level simulations. The prototype for our final parallel architecture runs at 500MHz and is capable of performing high-accuracy recognition of speech from the Wall Street Journal 60,000 word model at a speed 247.2 times faster than real-time while consuming less than 2W of power. To our knowledge, this is the most power efficient hardware architecture for speech recognition search that has been developed to date.