Low-power CMOS radio frequency integrated circuits for frequency synthesis.

摘要

With the minimum feature size in microelectronic devices reducing to deep submicron values, complementary metal-oxide semiconductor (CMOS) technology has become a viable choice for implementation of radio frequency (RF) integrated circuit (IC) building blocks. In addition, portable devices are required to operate for extended periods of time without the need to charge or change the battery, highlighting the importance of low power circuits. However, the reduction of the supply voltage demanded by hot carrier reliability and gate oxide breakdown concerns has caused many analog circuit solutions to be unsuitable for low power applications. Therefore, new circuit techniques and innovative design approaches are required to meet the stringent requirements of today's cutting edge wireless communication systems.; The phase-locked loop (PLL), or local oscillator (LO), is one of the most important building blocks to generate a reference frequency for wireless communication systems as it provides the timing basis for functions such as clock control, data recovery and synchronization. As the frequency of wireless communications extends to increasingly higher frequency bands, the generation of highly stable LO signals at low cost, becomes more and more challenging.; With the LO of a transceiver operating 90% of the time, the voltage-controlled oscillator (VCO) and frequency doubler (FD) are key components that require special consideration. This thesis focuses on the design, analysis and implementation of VCOs and FDs suitable for wireless applications. First, cross-coupled inductor-capacitor (LC) tank VCOs with frequency tuning provided using the back-gated voltages of the n-channel metal-oxide semiconductor (nMOS) cross-coupled differential pair in the oscillator core, are studied. VCOs with automatic amplitude control (AAC) are then studied that require, in addition to low power and low phase noise, a fast and reliable start up, allowing the oscillator to be set to its optimal bias point in terms of noise, while still biasing it with the maximum current at start-up, and allowing for a well defined level of output power, solving practical issues related to VCOs.; Next, the implementation of wideband FDs, which allows us to extend the nominal operating frequency of any VCO with only a slight degradation in phase noise, while allowing for integration in a system-on-chip (SoC) solution, are studied. The frequency doubler consists of two identical unbalanced source-couple pairs with different width over length W/L ratios, whose inputs are connected in parallel and its output taken single-ended. The design is based on the quadratic square-law characteristics of a metal-oxide semiconductor (MOS) transistor in saturation.; Finally, since accurate simulation results are of great importance in the design process, modeling of passive components are studied. In particular, since the resistor is used in many circuit for biasing purposes, a new n-well meander-line resistor model that can be used in circuit simulators, such as SPICE and SpectreRF and which is suitable for silicon RF ICs, is presented.