Re-configurable matrix multiplication.

摘要

Matrix multiplication is one of the fundamental arithmetic operations in digital signal processing applications and video graphics. This work emphasizes on architecture for matrix multiplication, which is dynamically reconfigurable with changing precision. The processor can be used to compute product of matrices Xnxk and Ykxm for any integers n, k, m and any precision b. For an input stream of h x h matrix pairs with b-bit items, on the proposed processor of size s = hb, the matrices Xnxk and Y kxm are partitioned into s/b x s/b sub-matrices. Thus trading array size with bit-width.; The processor consists of an array of 4 x 4 multipliers and adders as basic reconfigurable components. The control signal in the design is used as a reconfigurable switch for changing the bit-width of the matrix element. A major part of the architecture is symmetric and repeatable. The processor is pipelined to give desired output. Versatility of the architecture can be used for higher precision, varying sub-matrix size and the multiplier with maximal utilization of hardware available. With 4-bit multipliers and adders, the processor can be extended to 32-bit and 64-bit precision with sub-matrix size of 8 x 8 and 16 x 16 respectively.